1. Field of the Invention
The invention relates to a multi-layered printed wiring board (PWB), and more particularly to a multi-layered printed wiring board on which circuit elements such as a transistor, an integrated circuit (IC) and a large scale integrated circuit (LSI) are mounted.
2. Description of the Related Art
It is well know in the field that a multi-layered printed wiring board on which circuit elements such as a transistor, an integrated circuit (IC) and a large scale integrated circuit (LSI) are mounted generates electromagnetic noises which causes malfunction of an electronic device in which the multi-layered printed wiring board is incorporated or other electronic devices.
Such electromagnetic noises are quite often caused by radiation, which is so-called common mode, to be generated due to either a current to be generated by parasitic capacitance or parasitic mutual inductance of a circuit or a high frequency current to flow into a power supply line. Since the generation mechanism of the radiation is complicated, there was no effective measures to be taken in the vicinity of a radiation source. Thus, there has been conventionally used a metal box in which an electronic device is contained for electromagnetically shielding.
FIG. 1 illustrates one of conventional measures for preventing electromagnetic noise. There has been conventionally used a decoupling capacitor 4 connected in parallel with and in the vicinity of an IC/LSI 3 connected between a power supply line composed of a power supply line 16 and a ground line composed of a ground layer 17 of a printed wiring board. Herein, the IC/ LSI 3 is a source of high frequency power supply current. A high frequency power supply current generated due to switching operation of the IC/LSI 3 and running through the power supply layer 16 is bypassed to a ground through the decoupling capacitor 4 in the vicinity of the IC/LSI 3, in addition, voltage fluctuation at a power supply terminal of the IC/LSI 3, which is generated due to the switching operation of IC/LSI 3, being depressed.
The power supply line 16 acting as a power supply line in a conventional multi-layered printed wiring board is a complete planar layer composed of complete electrically conductive material such as copper. This maximizes a plane through which a current runs and thus minimizes electrical resistance in a power supply line, thereby providing the effect of depressing the fluctuation in dc power supply voltage.
However, the above mentioned conventional multi-layered printed wiring board has a problem that a designer cannot control a high frequency power supply current accompanied with the operation of IC/ LSI and flowing into the power supply layer through the decoupling capacitor.
Specifically, in a complete planar layer, since a power supply layer has a small impedance therein, a high frequency power supply current from an IC/ LSI flows into not only a decoupling capacitor disposed in the vicinity of a certain IC/LSI, but also decoupling capacitors disposed in the vicinity of other IC/LSIs. Thus, the high frequency power supply current was distributed quite complicatedly in an entire multi-layered printed wiring board, and hence it was very difficult or almost impossible to analyze the distribution of the high frequency power supply current. Accordingly, it was impossible to determine optimal capacitance of a decoupling capacitor associated with each of IC/LSIs.
Since the power supply layer makes a complete planar layer itself, a high frequency power supply current flowing into the power supply layer runs along complicated routes, and often forms a large loop, which might cause electromagnetic radiation and immunity degradation.
For instance, as illustrated in FIG. 2, suppose a circuit including an IC/ LSI 3c from which the greatest high frequency power supply current is to run, an IC/LSI 3d from which the second greatest high frequency power supply current is to run, and an IC/LSI 3e from which the smallest high frequency power supply current is to run, which IC/LSIs are connected to both a power supply line 16 and a ground line 17 in parallel. The illustrated circuit also includes a decoupling capacitor 4d disposed in the vicinity of the IC/LSI 3c and having the greatest capacitance and hence the smallest impedance Z, a decoupling capacitor 4e disposed in the vicinity of the IC/LSI 3d and having the second greatest capacitance and hence the second smallest impedance Z, and a decoupling capacitor 4f disposed in the vicinity of the IC/LSI 3e and having the smallest capacitance and hence the greatest impedance Z. The capacitance of these IC/LSIs is determined in accordance with a high frequency power supply current running from the IC/ LSIs 3c to 3e. This circuit has problems as follows.
Since the decoupling capacitor 4f disposed in the vicinity of the IC/LSI 3e has a greater impedance than the other decoupling capacitors 3c and 3d, for instance, all of high frequency power supply current derived from the IC/LSI 3e is not bypassed to the ground line 17 through the decoupling capacitor 4f, and thus a part of high frequency power supply current flows into the IC/LSI 3c or 3d, which makes a large current loop area. As a result, there may occur a problem that electromagnetic noises are increased, and accordingly the immunity is degraded.
In the case that the high frequency power supply current derived from the IC/ LSI 3e is not bypassed through the decoupling capacitor 4f disposed in the vicinity thereof, the introduction of the high frequency power supply current into other capacitors causes that an impedance is increased in a line where the high frequency power supply current is to run. As a result, the fluctuation in ac voltage is enlarged, which exerts a harmful influence on stable operation of the IC/ LSI 3e itself.
Thus, as explained earlier, there has been conventionally used a box in which an electronic device is contained for electromagnetic shielding. However, the metal box has to be formed with an opening through which the electronic device is handled. Accordingly, it was impossible to prevent external leakage of electromagnetic noises.
Japanese Unexamined Patent Publication No. 5-235679 published on Sep. 10, 1993 has suggested a printed wiring board in which at least one of ground patterns on a circuit board is made as a ground pattern to be used for a noise removing filter. The one of ground patterns is connected to a ground section of a circuit element located closest to a noise source.
Japanese Unexamined Patent Publication No. 4-302498 published on Oct. 26, 1992 has suggested a printed wiring board including insulating layers formed on circuit patterns and electrically conductive layers to be connected to a ground pattern, thereby preventing occurrence of radiation of high frequency noise derived from signal lines.
Japanese Unexamined Patent Publication No. 4-3489 published on Jan. 8, 1992 has suggested a method of forming transmission lines on a printed wiring board. The method includes the steps of forming a pattern on one of surfaces of a substrate, forming an insulating layer with which the pattern is covered, depositing an electrically conductive layer over the insulating layer to thereby define a transmission line with the pattern, insulating layers and electrically conductive layers, and removing copper foils deposited on the other surface of the substrate which foils may exert an influence on the transmission line.
Japanese Unexamined Utility Model Publication No. 4-43016 published on Apr. 13, 1992 has suggested a print filer comprising a film printed on upper and lower surfaces thereof in the form of coil and capacitor wiring patterns, and magnetic substances deposited on the upper and lower surfaces of the film to thereby establish a coil having a closed magnetic pass.
Japanese Unexamined Patent Publication No. 3-273699 published on Dec. 4, 1991 has suggested a printed wiring board having a through hole and a plurality of pattern surfaces, characterized by magnetic substance layers sandwiched between the pattern surfaces.
Japanese Unexamined Patent Publication No. 3-208391 published on Sep. 11, 1991 has suggested a hybrid integrated circuit parts in which a compound inductor composed of a layered structure of magnetic substance and conductive material and a compound capacitor composed of a layered structure of dielectric material and conductive material are overlapped to define a single-piece substrate. The substrate is formed with a recessed portion on which the electronic parts are to be mounted.
Japanese Unexamined Patent Publication No. 64-25497 published on Jan. 27, 1989 has suggested an inductance element including a first electrically conductive layer formed on an insulating substrate, a magnetic substance layer formed over the first electrically conductive layer, and a second electrically conductive layer formed on the first electrically conductive layer, covering the magnetic substance layer therewith.
Japanese Unexamined Patent Publication No. 63-300593 published on Dec. 7, 1988 has suggested a ceramic compound substrate comprising a first magnetic substance substrate having a certain magnetic permeability, a coil pattern made of electrically conductive material and printed on the first magnetic substance substrate, and having at distal ends internal electrodes to be connected to another circuit, and a second magnetic substance substrate formed on the coil pattern and cooperating with the coil pattern and the first magnetic substance substrate to establish an inductance element having a certain value of inductance.
Japanese Unexamined Utility Model Publication No. 61-173167 published on Oct. 23, 1986 has suggested a compound inductor substrate including a plurality of inductance elements composed of a layered structure of 8-figure shaped conductive patterns and magnetic substance layers, the inductance elements being arranged transversely of the FIG. 8s, the magnetic substance layer being formed with a groove extending transversely of the FIG. 8s across cross-points of the FIG. 8s.
Japanese Unexamined Utility Model Publication No. 61-38970 published on Mar. 11, 1986 has suggested a printed wiring board including a substrate, a pattern made of copper foil and formed over the substrate, first resist applied to cover the pattern therewith for isolation of the pattern, resin containing magnetic powder and applied on an upper surface of the first resist, and second resist applied on an upper surface of the resin.